
MAE Colloquium: Tiwei Wei (Purdue)
Ultra-dense 3D Chip/Packaging: Interconnect Materials and Thermal Management
Advanced semiconductor packaging is playing a crucial role in enhancing system performance and functionality. As computing demands continue to rise, particularly in emerging technologies, heterogeneous three-dimensional (3D) integration with fine-pitch, high-density interconnections, and multi-chip stacks offers significant promise for the future. 3D metal interconnects, such as through-silicon vias (TSVs), through-glass vias (TGVs), hybrid bonding and micro bumps, have enabled the development of several generations of high-bandwidth memory (HBM), which is critical for high-end computation applications, including graphics accelerators, network devices, datacenter AI ASICs, and FPGAs.For future memory-on-logic and logic-on-logic 3D integration systems, innovative semiconductor metal interconnect technologies will be essential to achieve ultra-high 3D interconnect densities ranging from 1E+6/mm² to 1E+8/mm². However, aggressive scaling of interconnect pitches and the use of nanoscale via interconnections present significant challenges in terms of process development and reliability. Furthermore, these high-density 3D integration systems lead to substantial increases in heat flux and power density (W/cm³), which generate thermal crosstalk and hotspots, causing non-uniform temperature distributions. High-performance, energy-efficient thermal management solutions are needed to tackle this thermal challenge.In this presentation, we will focus on two critical challenges in 3D integration technology: (1) Materials, Processing, and Architecture Development for Semiconductor Packaging, where I will share our latest research on the thermal, mechanical stress, and microstructure evolution behaviors in scaling 3D interconnects, as well as novel materials for vertical 3D interconnects; and (2) Heat Transfer in Semiconductor Devices and Advanced Packaging, which involves investigating nanoscale thermal transport phenomena at various levels, from the device level to the BEOL (Back-End-Of-Line), and extending to the chip and packaging levels. I will also present our recent work on direct-on-chip two-phase microfluidic cooling, near-junction cooling techniques, and the development of efficient thermal packaging materials designed for extreme thermal isolation and effective heat spreading.
Bio:
Tiwei Wei is currently an assistant professor of mechanical engineering at Purdue University. He was the postdoc research scholar in the NanoHeat lab at Stanford University between 2020 and 2022, working with Prof. Kenneth E. Goodson and adjunct professor Mehdi Asheghi. He received his Ph.D. degree at the Interuniversity Microelectronics Centre and KU Leuven, Belgium in 2020, under the supervision of Prof. Martine Baelmans and Dr. Herman Oprins. He joined imec in 2015, starting the Ph.D. research by developing electronic cooling solutions for high-performance systems. Before joining imec, he worked as a researcher staff at Tsinghua University and Hong Kong University of Science and Technology, from 2011 until 2015, with a focus on advanced microelectronic packaging techniques.